1. Field of the Invention
The present invention relates to an error detection/correction system and a controller using this system in a bus that connects modules of the control system with each other.
2. Description of the Related Art
In transmitting data, the data may include an error during the transmission. In order to detect and correct this data error, error detection/correction codes are used. In general, if an error detection/correction code has more inspection bits, then the detection/correction capacity becomes higher. If the unit for error detection/correction becomes larger, then the detection/correction capacity becomes higher when the ratio of the number of inspection bits to the number of information bits is the same.
On the other hand, the address and command portions of the bus transfer unit have a fixed length, while the data portion has a variable length. From this constraint, the size of a packet for error detection/correction is determined based on the minimum transfer quantity on a data side. In general, detection/correction capacity depends on ratio of inspection bits to information bits.
There is known a data error detection device (refer to Japanese Patent Application Laid-open No. 11-65944) in which, for coping with a variation in data quantity to be transmitted and received, a plurality of (k) ECC (error correction code) circuits (of n bits), which has been used when the number of output bits of the memory element is small, are used to detect an occurrence of trouble in the memory element, when the number of output bits of a memory element increases (to n×k bits).
In multiple starting points/multiple targets terminal unit switching system that exchanges messages via a fixed size burst or a cell, there is known a system in which each terminal unit generates an initial error correction code in a first burst of a message, a preceding burst error correction code, and an error correction code as a function of a burst data byte, and detects an error by comparing these generated error correction codes with a reception burst error correction code, thereby to secure the preservation of message exchanged between data processing terminals (refer to Japanese Patent Application Laid-open No. 6-53942).
In a method wherein data is divided into minimum units and an error is detected for each of the minimum data units in case where error detection is carried out for data of which length changes, the detection/correction capacity becomes constant. When the unit for error detection/correction becomes large, it is not possible to obtain the above-explained merit that, if the ratio of the number of inspection bits to the number of information bits is the same, the detection/correction capacity becomes higher when the unit for error detection/correction becomes larger.